This application claims the benefit of Korean Application No. 2000-60256, filed Oct. 13, 2000, in the Korean Industrial Property Office, the disclosure of which is incorporated herein by reference.
1. Field of the Invention
The present invention relates to a method of driving a plasma display panel, and more particularly, to an address-while-display driving method of driving an alternating current (AC) type triode surface-discharge plasma display panel.
2. Description of the Related Art
The structures of plasma display panels are largely classified into a counter-discharge structure and a surface-discharge structure depending on the arrangement of discharging electrodes. In addition, methods of driving a plasma display panel are classified into a direct current (DC) driving method and an AC driving method depending on whether the polarity of a driving voltage changes or not.
Referring to FIGS. 1A and 1B, discharge spaces 16 are formed between front glass substrates 10 and 1 and rear glass substrates 20 and 2 in a plasma display panel of DC type counter-discharge structure and a plasma display panel of AC type surface-discharge structure.
Referring to FIG. 1A, in the DC type plasma display panel, a scan electrode 18 and an address electrode 11 are directly exposed to the discharge space 16. Referring to FIG. 1B, in the AC type plasma display panel, display electrodes 3 for performing display are disposed within a dielectric layer 5 so that the display electrodes 3 (x-y electrodes) are electrically separated from the discharge space 16. Here, display is performed by a well-known wall-charge effect. For example, in discharge cells where discharge is provoked between an address electrode 8 and a scan electrode 3a, wall charges are formed around the address electrode 8 and the scan electrode 3a. Thereafter, a voltage lower than a discharge triggering voltage is applied between the scan electrode 3a and a common electrode 3b so that display can be performed only in discharge cells where wall charges are formed around the scan electrode 3a. Reference numeral 5xe2x80x2 denotes a dielectric layer covering the address electrode 8.
Referring to FIG. 2, address electrodes 8, dielectric layers 5 and 5xe2x80x2, X-Y electrodes 3, barriers 6 and magnesium monoxide (MgO) layer 9 as a protective layer are provided between a front glass substrate 1 and a rear glass substrate 2 in a usual AC type triode surface-discharge plasma display panel. A metal electrode 4 is used to increase the conductivity of each X-Y electrode 3.
The address electrodes 8 are formed to be parallel on the top surface of the rear glass substrate 2. The rear dielectric layer 5xe2x80x2 is deposited on the entire surface of the rear glass substrate 2 having the address electrode lines 8. The barriers 6 are formed on the surface of the rear dielectric layer 5xe2x80x2 such that the barriers 6 are parallel to the address electrodes 8. The barriers 6 define the discharge areas of discharge cells and prevent optical cross talk between the discharge cells. A phosphor layer 7 is formed between the barriers 6. The phosphor layer 7 generates light having a color (red, green or blue) corresponding to ultraviolet rays generated due to the discharge of each discharge cell.
The X-Y electrodes 3 are formed on the bottom surface of the front glass substrate 1 such that the X-Y electrodes 3 are perpendicular to the address electrodes 8. The X-Y electrodes 3 cross the address electrodes 8 to form the discharge cells. The front dielectric layer 5 is deposited on the entire bottom surface of the front glass substrate 1 having the X-Y electrodes 3. The MgO layer 9, which protects the display panel from an intensive electric field, is deposited on the entire surface of the front dielectric layer 5. Gas for forming plasma is sealed in a resulting discharge space.
FIG. 3 illustrates a typical address-display separation driving method for the AC type triode surface-discharge plasma display panel of FIG. 2. FIG. 4 illustrates the interconnections between electrodes 3 that perform the driving method of FIG. 3 in the plasma display panel of FIG. 2. Reference numerals 3a and 3b of FIG. 4 denote the X-Y electrodes 3 of FIG. 2.
Referring to FIGS. 3 and 4, a unit frame (i.e., a unit television field) is divided into 6 sub-fields SF1 through SF6 to realize time division gradation display. In addition, each of the sub-fields SF1 through SF6 is divided into address periods A1 through A6 and display periods S1 through S6.
During each of the address periods A1 through A6, a display data signal is applied to address electrodes AR1, AG1, AB1, . . . , AGn and ABn, and simultaneously, corresponding scan pulses are sequentially applied to Y electrodes Y1 through Y480. Accordingly, when the display data signal of a high level is applied while scan pulses are being applied, wall charges are formed in corresponding discharge cells due to an address discharge. In discharge cells other than the corresponding discharge cells, wall charges are not formed.
During each of the display periods S1 through S6, a display pulse is alternately applied to all the Y electrodes Y1 through Y480 and the all X electrodes X1 through X480 so that display is performed in discharge cells where wall charges are formed during each corresponding address period A1, . . . or A6. Therefore, the luminance of a plasma display panel is proportional to the time of the display periods S1 through S6 in a unit television field.
Here, the display period S1 of the first sub-field SF1 is set to a time 1T corresponding to 20. The display period S2 of the second sub-field SF2 is set to a time 2T corresponding to 21. The display period S3 of the third sub-field SF3 is set to a time 4T corresponding to 22. The display period S4 of the fourth sub-field SF4 is set to a time 8T corresponding to 23. The display period S5 of the fifth sub-field SF5 is set to a time 16T corresponding to 24. The display period S6 of the sixth sub-field SF6 is set to a time 32T corresponding to 25. Consequently, among the 6 sub-fields SF1 through SF6, a sub-field to be displayed can be appropriately selected so that gradation can be realized.
FIGS. 5A to 5F illustrate driving signals in the unit sub-field SF1 according to the address-display separation driving method of FIG. 3. In FIGS. 5B to 5F, reference character SAR1, . . . , ABn denotes a driving signal applied to the address electrodes AR1, AG1, . . . , AGn and ABn of FIG. 4, reference character SX1, . . . , X480 denotes a driving signal applied to the X electrodes X1 through X480 of FIG. 4, and reference character SY1, . . . , Y480 denotes a driving signal applied to the Y electrodes Y1 through Y480 of FIG. 4. Referring to FIG. 5A, the address period A1 in the unit sub-field SF1 is divided into reset periods A11, A12 and A13 and a main address period A14.
During the display period S1, a display pulse 25 is alternately applied to all the Y electrodes Y1 through Y480 and all the X electrodes X1 through X480 so that display is performed in discharge cells where wall charges are formed during the corresponding address period A1. When a final pulse is applied to the X electrodes X1 through X480 during the display period S1, electrons are formed around X electrodes of selected discharge cells for display and positive charges are formed around Y electrodes thereof. Accordingly, during the first reset period, a pulse 22a having a lower voltage and larger width than the display pulse 25 is applied to the X electrodes X1 through X480 so that discharging for primarily removing wall charges is performed. In addition, during the second reset period A12, a pulse 23 having the same voltage as and a smaller width than the display pulse 25 is applied to all the Y electrodes Y1 through Y480 to discharge and also remove the remaining wall charges. During the third reset period A13, a pulse 22b having a lower voltage and a larger width than the display pulse 25 is applied to the X electrodes X1 through X480 to discharge and finally remove the wall charges. Consequently, all the wall charges can be removed from the discharge space, and space charges can be uniformly distributed.
During the main address period A14, a display data signal is applied to the address electrodes AR1, AG1, . . . , AGn and ABn, and simultaneously, a scan pulse 24 is sequentially applied to the Y electrodes Y1 through Y480. For the display data signal applied to each of the address electrodes AR1, AG1, . . . , AGn and ABn, a positive polarity voltage Va is applied when selecting a discharge cell, but otherwise, a ground voltage, i.e., 0 V, is applied. A bias voltage of positive polarity is applied to the Y electrodes Y1 through Y480 while scan is not performed, and the scan pulse 24 of 0 V is applied thereto while scan is being performed. Accordingly, when the display data signal is applied while the scan pulse 24 of 0 V is being applied, wall charges are formed in corresponding discharge cells due to address discharge but are not formed in other discharge cells. Here, to realize more accurate and efficient address discharging, a bias voltage lower than that of the display data signal is applied to the X electrodes X1 through X480.
According to such an address-display separation driving method, since the time domains of the sub-fields SF1 through SF6 of FIG. 3 are separated in a unit television field, the time domains of the address period and the display period are separated in each of the sub-fields SF1 through SF6. Accordingly, each pair of X and Y electrodes which have been addressed is in a stand mode until the remaining pairs of X and Y electrodes are all addressed during the address period. Consequently, an address period is longer and a display period is relatively shorter in each sub-field so that the luminance of light emitted from a plasma display panel is lowered.
To solve the above and other problems, it is an object of the present invention to provide a method of driving a plasma display panel using address-while-display driving method, through which the accuracy of address discharging increases, thereby improving the picture quality of the plasma display panel and decreasing the power consumption thereof.
Additional objects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
Accordingly, to achieve the above and other objects of the invention, a method of driving a plasma display panel having opposing front and rear substrates which are spaced facing each other, parallel X and Y electrodes formed between the front and rear substrates, and address electrodes formed to cross the X and Y electrodes so that discharge cells are defined by the crossing X and Y electrodes and the address electrodes, the method according to an embodiment of the present invention including periodically applying display pulses to all the X and Y electrodes, initializing discharge conditions of a previous sub-field, and sequentially forming wall charges at discharge cells to be displayed in a current sub-field while the display pulses are not applied, where a bias pulse having the same polarity as and a lower voltage than the display pulses is applied to all the address electrode lines while the display pulses are applied.
According to an aspect of the present invention, a bias pulse having the same polarity as and a lower voltage than the display pulses is applied to all the address electrodes while the display pulses are applied to reduce movement of space charges from the discharge cells where display discharging is provoked by the display pulses to adjacent other discharge cells (i.e., the probability that address discharging is provoked so as to form wall charges at discharge cells where wall charges should not be formed at the address step can be reduced) so that the accuracy of address discharging is increased in driving a plasma display panel according to an address-while-display driving method, thereby improving the picture quality of the plasma display panel and reducing the power consumption.
According to another aspect of the present invention, the voltage of the bias pulse applied to all the address electrodes is the same as or lower than the voltage of a data pulse which is applied to selected address electrodes during the sequentially forming the wall charges.
According to a yet another aspect of the present invention, the bias pulse is applied to all the address electrodes only while the display pulses are applied to all the Y electrodes, and during the sequentially forming the wall charges, a data pulse is applied to selected address electrodes, and simultaneously, a scan pulse having a polarity opposite to that of the data pulse is applied to a corresponding single Y electrode line so that wall charges are formed at discharge cells to be displayed.